Modern digital data processors, such as Digital Signal Processors (DSPs), are being applied in numerous different types of applications, including broadband communications, medical-imaging equipment, modems, audio equipment, motor control and others. One important application that is of most interest to the teachings of this invention is in the field of wireless telecommunications, such as cellular telephones and personal communications, referred to herein generally as wireless terminals. Other applications of interest include base stations for wireless terminals, as well as internet computing.
One approach to designing a modern wireless terminal is to employ application specific integrated circuit (ASIC) technology and/or Field Programmable Gate Array (FPGA) technology. In the ASIC approach the required circuit blocks are embedded within one or more custom designed ASIC packages. However, the ASIC approach generally requires significant design and manufacturing lead times. Furthermore, once the design(s) are committed to circuits subsequent changes become difficult or impossible to make in a rapid and cost-effective manner. The FPGA approach, while somewhat more flexible than the use of ASICs, is generally a “fine-grained” solution that enables reprogramming for certain circuit blocks. While the fine-grained nature of the FPGA makes it flexible and programmable, this is achieved at the cost of high silicon overhead, which can be a disadvantage in cost-sensitive applications.
To avoid or at least reduce the risk inherent in the ASIC and FPGA (high cost) approaches many designers prefer to use the DSP approach, wherein one of a number of commercially available DSPs is selected based on some criteria. Once selected, the design task becomes primarily one of programming the DSP, for a typical wireless terminal application, to perform the required functions, such as filtering and Viterbi decoding. If subsequent changes in design are required then, ideally, the changes are limited to software (firmware) revisions, and do not impact any physical circuit(s).
There are a number of commercially available DSPs that are currently marketed by a various integrated circuit manufacturers. One current list can be found in an article by Marcus Levy entitled “DSP-architecture directory”, EDN, Mar. 30, 2000, pgs. 60–96.
One drawback to the use of DSPs is that most are designed to provide an overall functionality that is applicable to a number of different types of applications. Because of this generality, no one specific DSP may be ideally suited for a specific application. For example, a DSP that is designed so as to serve both the audio reproduction and the motor control markets may not be ideally suited for use by either, requiring some tradeoffs in performance and ease of use.
It is known in modern DSPs to provide certain processing resources or elements that can be selectively utilized in more than one way. For example, the TMS320C5000™ DSP that is available from Texas Instruments provides an Arithmetic Logic Unit (ALU) that can be used to operate on 32-bit data or split to perform dual 16-bit operations. A C54x version of this DSP provides a 40-bit adder at the output of a multiplier to enable unpipelined Multiply and Accumulate (MAC) operations, as well as dual addition and multiplication in parallel.
A REAL™ DSP available from Philips Semiconductor features a dual Harvard architecture with two 16-bit data buses connected to a data-computation unit (DCU). Each ALU in the DCU operates on 32-bit data and eight overflow bits and stores the results in four, 40-bit accumulators. A feature of this DSP is that each 32-bit ALU may be split into two 16-bit ALUs.
Another DSP available from Texas Instruments (TMS320C6000™) lacks a dedicated MAC unit, and instead performs MAC operations by using separate multiply and add instructions. The architecture of this DSP includes dual datapaths and dual matching sets of four functional units. The total of eight functional units include two multiply (M) units and six 32-bit arithmetic units with a 40-bit ALU and a 40-bit barrel shifter. The multiply units can perform two 16×16-bit multiplies every clock cycle, or four 8X8-bit multiples.
The TigerSharc™ DSP available from Analog Devices provides two computation blocks enabling two 32×32-bit MACs per cycle or, when operating on 16-bit data, eight 16×16-bit MACs per cycle. Each computation block includes a register file of 32, 32-bit registers that are combinable (two 32-bit registers to form one 64-bit register, or four 32-bit registers to form a single 128-bit destination register for the multipliers).
Finally, Module Research Center provides a NeuroMatrix™ NM6403™ DSP having a 32-bit Reduced Instruction Set (RISC) core and a 64-bit Vector coprocessor. In this DSP the number of MACs per processor cycle depends on the length and number of words packed into a 64-bit block, and the configuration of the engine can change dynamically during calculations. That is, an application can be started with maximum precision and minimum performance, and the performance can then be dynamically increased by reducing data-word lengths.
From the foregoing non-exhaustive list of currently available DSPs it can be appreciated that a certain level of flexibility has been provided to more efficiently use the resources of the DSP. For example, multipliers and ALUs can be split and registers can be combined depending on the length of data-words being operated upon. An ability to dynamically change data-word length is also currently possible to achieve.
A trend is also developing to provide DSP users with an ability to design their own DSPs using DSP generator tools. One example of a currently available DSP generator is known as a Transport Triggered Architecture from the Technical University of Delft. Reference can also be had to a publication entitled “Microprocessor Architectures from VLIW to TTA”, by Henk Corporaal. In the user-generated DSP architectures it can be expected that techniques to optimize the use and re-use of hardware elements will also be an important consideration.